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Managing Wafer Retest | EX0-113 exam Braindumps and Study Guide

every wafer test touch-down requires a balance between a pretty good electrical contact and combating hurt to the wafer and probe card. achieved wrong, it can destroy a wafer and the custom-made probe card and result in negative yield, in addition to failures within the container.

reaching this stability requires good wafer probing manner strategies as well as monitoring of the resulting process parameters, a whole lot of it unseen with the aid of the outside world. The mechanical finesse and metallurgical complexity of wafer checking out is broadly speaking hidden from design, design for verify (DFT), and even product engineers making a product’s check approach and look at various content material. however that doesn’t make it any much less important. without a cautiously engineered and controlled wafer touchdown system, tests cannot be utilized correctly. If the touch-down is simply too easy, the verify records could be incomplete. If it’s too complicated, it may well harm the tiny circuits.

“The least-understood have an impact on of wafer probe is interaction between the wafer probe tip’s genuine have an impact on on energetic circuits below the pad/bump and upstream packaging methods,” stated George Harris, vice president world examine services at Amkor technology.

Getting this incorrect can lead to disasters in the fab and within the box. “There’s all these competencies lengthy-time period reliability issues linked to extreme probing,” defined Jerry Broz, senior vp of technology construction at foreign look at various options. “It might crack pads and affect bondability right through assembly. excessive probe mark depth and punch via may damage circuits below the pads resulting in an infantile failure or a walking wounded device.”

due to product requirements, an IC equipment may also acquire distinctive wafer checks at several temperatures. It additionally may well be retested to recover yield. This frequently occurs due to unsuitable wafer examine phone setup or unexpected considerations with the probe card, which requires a verify flooring operator/technician to investigate.

“Retest is legitimate and a good idea if it is concerning a look at various setup problem, but now not if the machine is in reality bad,” referred to Greg Prewitt, director of Exensio solutions at PDF options. “Yield issues can point to unhealthy probe cards, look at various plan setup problems, or gadget balance issues,”

by means of monitoring a number of gadget test and device statistics, verify factories can proactively manage the wafer check manner to instantly identify yield concerns and instantly verify if it’s a product or wafer examine phone problem. The decisions made from such statistics gives inputs into the manufacturing execution system (MES). With yield management programs, fabless corporations additionally video display wafer verify facts for retests to extra accurately figure a fab difficulty from a verify operations setup subject.

trying out contains an electrical-mechanical connection. Mechanical actuation creates the genuine contact that permits the electrical connection for transmitting vigour and alerts to the machine undertest. it's a since the pad or bump will adventure some deformation, such as scrub marks. Minimizing this deformation informs the engineering specifications for x, y, z prober handle on the order of tens of microns.

Deformation also occurs to the probe assistance, making them less than most beneficial with each and every landing. To lower this normal have an impact on, periodic cleaning of a probe card’s probe tips occurs. Prober machine makes use of an automatic cleaning system which requires a clean of the probe assistance after Y quantity touchdowns, where Y can latitude from 20 to one hundred touchdowns.

Probe device, cleansing processing and manufacturing video display information all assist minimizing test mobile concerns. The probe card is the place the examine sign meets the gadget beneath check (DUT). Probe card producers assist diverse engineering requirements, including electrical verify, operational efficiencies, and mechanical realities of the wafer probing procedure.

Wafer probe basicsWhen engineers generate ATPG patterns, architect a BiST scheme for a posh SoC, or develop analog-to-digital converter look at various content, they have got an image of a wire between the DUT and ATE. What is not obvious is that it takes an important amount of mechanical and metallurgical engineering to create that wire.

On a producing look at various flooring, technicians and operators insert wafer a great deal (typically 25 wafers), or packaged unit lots, into test cells. those test cells are composed of the ATE, prober/handler, probe card/loadboard, and linked product examine software. The examine telephone supports repetitive running of the test program on every DUT. To deliver alerts and vigor to the DUT, a metal-to-steel contact has to be made between the DUTs pads/pin and interface hardware. For wafer test (sort or probe), this interface hardware is called a probe card, and prober gadget manages the physical method of touching a probe tip onto a die pad/bump.

believe first the mechanical handling features of constructing a fine contact.

“From a positional error stack-up here is an exceedingly elaborate issue,” talked about ITS’ Broz. “These pads are 40 via 50 microns square or smaller. feel about a one contact DRAM entire wafer probe card by which a hundred and twenty,000 probes landing on a hundred and twenty,000 pads, all at the equal time with the identical over go back and forth. this may require a better than 25 micron planarity window across 300 millimeters in a prober, which is creating about 450 kgs of drive (i.e., 1 to 2 grams of drive per probe tip).”

Now, believe the metallurgy necessities. depending upon the following packaging technology, a probe card’s probe tip touches both a pad or a C4 bump, or micro-bump. for many wire-bond applications, the pad is made of aluminum or copper. In flip-chip packaging, C4 bumps latitude in their metallurgical compositions. while fabs and examine flooring have clean/semi-clean rooms, the individuals working in these amenities want oxygen and oxygen mixed with any metallic creates an oxide. This oxide impairs the intermetallic contact fundamental for an electrical test with every landing.

the necessity of breaking through the oxide requires the probe card to go beyond touching the pad/bump — typically as a whole lot as 50 microns. This over-travel consequences in a scrub mark on the pad/bump. Some product sectors requiring distinct temperature checking out at wafer type. To restrict pad enviornment hurt, engineers purpose to have the equal scrub place touched. The smaller the scrub mark’s area, the much less likely it will impact the die-to-equipment connect manner.

Fig. 1: Wafer probe steps to create an intermetallic contact. source: Semiconductor Engineering/Anne Meixner

achieving high planarity throughout the probe card tips and probed die/dies reduces the volume of overtravel and hence reduces the scrub mark area and depth.

Planarity described the adaptation in the vertical distance (z route) between the pads and the probe counsel. Prober equipment usually uses optical alignment to investigate planarity version. The prober applies the overtravel distance handiest in spite of everything probes make a mechanical contact does, assuring a fantastic electrical contact.

holding everything aligned is an paintings, and things get greater complicated with diverse temperature checking out.

probably the most basic factor in the probe card is the probe itself, and probe varieties range from cantilever to vertical springs and vertical MEMS. The design considerations consist of the product’s pad dimension and pitch, latest ability, and temperature latitude. Probe material residences inherently influence the touchdown metallurgy, existing carrying skill and coefficient of thermal expansion (CTE).

CTE at once impacts probe tip to pad/bump alignment, which ripples out to general operation effectivity (OEE) of the verify manufacturing facility, in addition to product reliability.

Fig. 2: DRAM probe card. source: FormFactor.

“in case you scrub too an awful lot there’s a reliability subject,” pointed out Alan Liao, product advertising and marketing director for FormFactor’s probes business unit. “Most customers have between a forty five-to-fifty five micron to 60-via-80-micron pad enviornment (wire-bond product), and they need a minimum scrub mark. With multiple touchdowns every in diverse temperature environments, client’s number one challenge is touchdown accuracy. Temperature impacts the alignment manner because of CTE ameliorations between the probe card and wafer. accomplishing the optimum thermal equivalent state can take two or extra hours. No manufacturing facility can wait that long, so then it becomes a tradeoff. can you make the alignment decent ample, plus or minus 5 microns, as an example? which you can apply some system design expertise and use a pre-calculated probe position for different temperature situations so that you can meet alignment requirements as quickly as possible.”

The forces applied to a wafer raise as diverse sites are added to the probe card. those deserve to be monitored. examine outcomes for open contacts indicate advantage probing considerations.

“At wafer check your probe card commonly has distinct test sites to allow parallel check — 4, 16, 32, or greater. Having a homogeneous drive throughout all the probes over the entire die is a very crucial parameter,” defined Stéphane Iung, senior manager applications in silicon lifecycle analytics at Synopsys. “If there exists inhomogeneous power, it will probably lead to contact screw ups on one or more verify websites, so that’s basically critical to monitor. To make amends for that challenge, to make sure that the contact great is respectable, operators may additionally provide bigger over-go back and forth. but over-travel can lead to pad harm, a sort of a pernicious side impact of attempting to repair the primary impact with the aid of greater over-shuttle. That doubtlessly ends up in degradation of the die.”

Monitoring and managing touchdowns qualityContact failure is monitored through an electrical dimension of contact resistance.

Probe card designers, wafer look at various engineers, and look at various flooring technicians assess the high-quality of the intermetallic contact by using measuring contact resistance, or CRES. This parameter units recipes for overtravel, cleaning cycles, and examine display screen alarms for detecting considerations with the look at various/prober set-up. When the contact resistance becomes too high it adversely affects the signals between the ATE and the DUT as neatly as the vigor delivered to the DUT. This may end up in both hurt to the DUT or probe card and impairs distinguishing between decent and bad die with the check software.

fortunately, CRES can also be measured in every die confirmed. it is calculated early in the wafer check application all over the opens and shorts checks carried out on I/Os. These assessments investigate the contact integrity just before powering up and deliver protection to the DUT, ATE and probe card from damage. Most I/Os have ESD insurance policy diodes, which look at various engineers to make use of for his or her contact resistance dimension. the most average method is to supply two different currents, measure the resulting voltages to deliver you the time-honored slope of Ohm’s legislation (i.e. R=V/I). CRES can also be measured per sign pin.

Over assorted touchdowns, wafer check processes can computer screen the suggest and normal deviation of CRES. check flooring operations use CRES monitoring as a manufacturing statistical manner control parameter. In establishing probing technology a module engineer sets a CRES specification per semiconductor method expertise. Now each time a probe card touches a die it receives a little bit dirty, and dust raises contact resistance. To hold the CRES goal periodic cleansing is performed.

“Probe cards utilized in wafer-variety latitude from very basic designs to particularly engineered ‘correct by construction’ applied sciences which are constructed the use of semiconductor-like 2d and 3D MEMS strategies,” talked about Broz. “No single probe or probe card know-how solution matches to address all of the device checking out requirements. however, all probing solutions (no depend how superior) have to be cleaned all over wafer test to keep their efficiency.”

With dissimilar probes on the same die, engineers want each subsequent contact-down to touch down in the equal region. This minimizes the influence on the wire-bond die attach manner. The more untouched pad enviornment, the greater successful the wire-bond connect method. this is so essential that industries with high sensitivity to reliability-related failures, comparable to automotive, avert the number of wafer contact-downs.

therefore monitoring components that cause excessive contact failures is a component of each check floor operations.

To mitigate the administration of the probing procedure a larger number of parameters to computer screen and manage testify to the mechanical electrical engineering complexity of the method. Amkor’s Harris listed the following:

  • Re-probe count;
  • Stepping past exclusion zones;
  • Chuck motion accuracy — X, Y, and Z and rotation;
  • Electrical contact resistance and location to site adaptations;
  • actual dimensions of the probing cloth (size/width dimension min/max);
  • Planarity;
  • Alignment;
  • Angles of incidence, and
  • Spring features over time.
  • “These control parameters are actively measured the usage of prior and post-check processes, in addition to in-situ and real-time within the look at various processes with old SPC limits and predictive analytic methodologies,” observed Harris.

    With these parameters, look at various ground engineers and technicians computer screen probe card fitness for off-line preservation as a result of sudden alternative is expensive — and not simply in dollars.

    “if they need to substitute the cardboard, that’s the place it receives expensive,” noted Keith Schaub vice president of technology and method at Advantest the us. “more importantly, this influences time-to-market as a result of now they must order this probe card. It must be assembled. It has to be calibrated. It must be verified. This all takes time.”

    The order to ship time is frequently six months. This motivates keeping probe card health. automatic cleansing on the verify telephone is one maintenance part. The other is average inspections with a probe card analyzer. examine floor operations with a excessive mixture of items can use the check phone alternate over to operate commonplace inspection and renovation.

    “With a probe card analyzer, a technician can search for both electrical and mechanical changes,” spoke of Darren James, technical account supervisor at Onto Innovation. “This contains electrically checking resistance of the connects, checking resistor and capacitor values on the probe card, checking relays. It also comprises mechanically checking the vicinity of the probe tip in X, Y, and Z, each free putting and at over-go back and forth, checking probe force, checking probe planarity for no bused pins (an electro-mechanical look at various).”

    As check floors innovate with industry 4.0 applied sciences, the capability to proactively determine impending problematic probe card can enhance each operational efficiencies and verify program measurement accuracy.

    “Degraded yield/throughput is indicative of a failing or broken probe card or load board,” observed PDF solutions’ Prewitt. “with out an information analytics answer in area, the degradation can persist for a protracted period of time before it is observed or resolved through standard protection strategies.”

    ConclusionAs with the assembly method, the mechanical and metallurgical challenges in wafer probing require high-quality inter-steel contacts that ensure the stream of electrons. however for a package this is a one-time connection, whereas in wafer probing this must ensue many times. For a die, this may well be as few as three or as many as six times, and it may well contain dissimilar temperatures and re-probing due to poor electrical contact. For a probe tip, it’s on order of tens of heaps of touch-downs.

    Engineering teams on the look at various flooring actively control the wafer touch-down system and display screen distinctive parameters from the test gadget and wafer look at various outcomes. With analytic systems for each test and manufacturing unit equipment, statistics engineers and technicians proactively can reply to degrading contact resistance, use clever probing systems to satisfy touch-down limits, and reduce harm to product and probe cards.

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