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OMG OMG-OCUP-100 : OMG-Certified UML Professional Fundamental Exam

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Exam Number : OMG-OCUP-100
Exam Name : OMG-Certified UML Professional Fundamental
Vendor Name : OMG
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OMG-OCUP-100 test Format | OMG-OCUP-100 Course Contents | OMG-OCUP-100 Course Outline | OMG-OCUP-100 test Syllabus | OMG-OCUP-100 test Objectives

Examination Number: OMG-OCUP-100
Duration: 120 minutes for residents of English-speaking countries; 150 minutes for all others
Minimum Passing Score: 60 items correct out of 90
Prerequisite: None

The Class Diagram 25%
The Object Diagram 5%
The Package Diagram 5%
The Use Case Diagram 5%
The Activity Diagram 20%
The Sequence Diagram 15%
The State Machine Diagram 10%
TOTAL 100%

Common Structure
• Type
• Dependency
• Namespace
• VisibilityKind (public, private, protected)
• MultiplicityElement
• Constraint
• Comment
• PackageImport

• Package (NOTE that Package Merge is not covered in OCUP 2)

Simple Classifiers
• PrimitiveType
• DataType
• Enumeration
• EnumerationLiteral
• Interface
• InterfaceRealization
• Signal
• Reception

Structured Classifiers
• Association
• Class

• Generalization
• Feature
• Structural Feature
• Behavioral Feature
• Property
• Operation
• Parameter
• AggregationKind
(Composition, Aggregation)
• InstanceSpecification
• Slot

• LiteralBoolean
• LiteralInteger
• LiteralReal
• LiteralUnlimitedNatural
• LiteralNull
• LiteralString
• Opaque Expression

Use Cases
• UseCase
• Actor
• Include
• Extend

• Interaction
• OccurrenceSpecification
• ExecutionSpecification
• ExecutionOccurrenceSpecification
• DestructionOccurrenceSpecification
• Lifeline
• Message
• MessageOccurrenceSpecification
• MessageSort
• MessageEnd

Common Behavior
• CallEvent
• SignalEvent
• Trigger
• OpaqueBehavior

• Activity
• ActivityFinalNode
• ActivityParameterNode
• ControlFlow
• InitialNode
• DecisionNode
• FlowFinalNode
• ForkNode
• JoinNode
• MergeNode
• ObjectFlow
• ObjectNode

• Action
• CallBehaviorAction
• CallOperationAction,
• SendSignalAction
• AcceptEventAction
• Pin
• InputPin, OutputPin
• OpaqueAction

State Machines
• StateMachine
• State
• Transition
• Pseudostate: choice, junction, initial
• FinalState

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OMG UML testing

Accelerating excessive-degree SysML and SystemC SoC Designs | OMG-OCUP-100 PDF Braindumps and test dumps

through Waseem Raslan, Mentor pictures EgyptAhmed Sameh, The American university in Cairo


SysML, the dedicated device degree UML-based mostly notation proposed via the OMG, is gaining a lot of momentum as a gadget stage design common. Design productivity is among the main challenges dealing with the semiconductor design roadmap for >= 32 nm know-how as cited by the ITRS. increasing the level of abstraction and automation are two of the methodologies suggested with the aid of the ITRS to address the design productivity problem. Producing executable requisites is an additional methodology to increase the productiveness. This analysis suggests that the automated mapping of SysML, the gadget stage UML primarily based notations adopted by the OMG to SystemC, that became standardized by means of the IEEE, can raise the level of design abstraction in an automatic ambiance and produce executable files.


In its 2005 design report, ITRS [20] has listed a couple of challenges which are dealing with the EDA design within the near future. amongst these challenges changed into the should raise the design productivity. raising the degree of design abstraction is one key design methodology that has been counseled by the ITRS to beat the design productivity problem.

electronic Design Automation, EDA, equipment are very effective at the register switch level of abstraction and the abstraction degrees under. Being designated and sluggish by nature, these levels of abstraction don't seem to be relevant for validating an entire system that may be extra implemented in utility or hardware. In today’s tight schedules and difficult time to market competitors, the means to validate the entire gadget at a more robust stage of abstraction is fitting a mandatory for designers to stay away from disagreeable surprises at vital phases of the system integration. rising equipment level languages, like SystemC and SystemVerilog, have erupted to elevate the degree of abstraction stage above the RTL one. Yet these languages nonetheless have upper boundaries in terms of visual descriptions and ease of use at the gadget level. additionally, Martin shows in [5] that these new languages can not, with the aid of themselves, be used to close the gap between hardware and application designers.

UML has been the software notations normal for years and has been generally adopted and used for the utility group. a number of researches have recommended that UML, in particular after its 2.0 standard, may be used as a hardware requirement and description notation as neatly. due to the fact that SystemC is considered the language that may well be optimal used for describing the gadget at a very excessive level of abstraction, and because it be a C++ based library, SystemC is regarded the natural language to observe the UML in the abstraction degree hierarchy. in addition, SystemC models produces an executable that can also be run to simulate the system it models. If SystemC is modeling a system at a really excessive stage of abstraction, this executable can also be regarded the executable specification of the device, which is without doubt one of the methodologies which are recommended via the ITRS to handle the design productiveness problem. due to the fact that elevating the automation level is without doubt one of the methodologies advised by way of the ITRS to beat the productiveness problem, computerized translation from UML to SystemC has been a hot of area of research in the ultimate four years. a few gadget level UML profiles have proposed in the context of these researches.

Realizing the importance to standardize these system level notation profiles, a request for thought, RFP, have been presented to the OMG community to standardize a device stage UML profile that will also be most appropriate used to model a system. SysML has been proposed for the OMG group and its 1.0 draft revision has an excellent capabilities to become the regular system level UML profile. The purpose of this analysis is to analyze the mapping between SysML and SystemC, propose and suggest the SystemC modeling concepts that should outcomes in modeling both the structure and behavioral SysML diagram to supply a single executable that represents the equipment behavior. A prototype for a translation tool, a SysML model compiler, has been carried out the usage of a UML modifying tool that helps SysML. Un-timed TLM SystemC fashions had been generated to mannequin the anticipated conduct of the SysML.This paper is equipped because it follows: part 2 presents linked work to this analysis, part three items the prototype that has been carried out, section 4 gifts the mapping between SysML and

SystemC via a practical SysML example, and at last conclusions and future work are presented in part 5.

1. linked WORK

Thiagarajan et al. have proposed a equipment in [18] that parses the UML design made out of Rhapsody device in its XMI layout to provide an abstract tree of the design that is fed to the pace template based code generation engine. The proposed device is fed additionally with a group of SystemC templates to generate the SystemC code based on them. Their work turned into notably concentrated on the classification and state chart diagrams.

In a later analysis, Thiagarajan et al. have proposed a gadget in [16] which they've referred to as RT2SystemC translator. in this research, they have got used Rational Rose real Time UML enhancing device to mannequin the complete equipment. To generate the SystemC code, the C++ generated code from Rational Rose changed into converted into XML using the GCC_XML utility. The XML output is then preprocessed and parsed the use of JDOM, then translated into SystemC code.

Prevostini et al. have proposed in [9] the ACES design move it's a complete design circulate that begins from the UML degree. ACES design move grabs the device requirements in the course of the type, state computer, endeavor, sequence and use case diagrams edited by the Rhapsody device. Then extracts the feature and constitution tips via traversing Rhapsody information model, accessed via Rhapsody APIs, to generate the SystemC models. ACES design movement takes the SystemC generated code down the style in the course of the application, hardware and interface synthesis system.

In an try to create a proper bridge between UML and SystemC, Snook et al. have proposed in [13] translating UML design into the formal B language where formal B validation equipment may also be applied to the design. This step became carried out by means of creating a tool called U2B. After validating the design within the B area, it’s translated to SystemC the usage of a created tool referred to as B2SystemC. Snook et al. have created a really expert UML profile referred to as UML-B and focused their work on the equipment, classification and state chart diagrams.

Mellor et al. have proposed in [6] an executable and translatable equipment that enables the designers to model debug, and validate their UML mannequin via model execution in spite of the exact implementation. After mannequin validation, the mannequin gets translated into algorithmic C or C++ via making use of a set of translation suggestions on it. Mellor et al. are convinced, [7],that best the class, state chart and the motion diagrams are fair adequate for modeling hardware. furthermore they're convinced that round go back and forth engineering is not necessary during this selected design area, i.e. generated code shouldn’t be manually edited via the designers. The generated algorithmic C or C++ code is then fed to the synthesis equipment that are in a position to enforce the hardware a part of the gadget.

different researches were conducted concentrated on SystemC code generation targeting primarily the type and state desktop diagrams as in [19], [10], [11], [12] and others. all the outdated translators were targeting a subset of the UML diagrams, especially type diagrams and state desktop diagrams, the usage of a proposed UML profile to healthy equipment level modeling. The existing research is targeting SysML profile proposed by means of OMG to be the device degree average. The present analysis isn't specializing in selected diagrams. On the opposite this analysis is trying to advantage from most of the SysML diagrams during the SystemC transformation phase.

all of the previously related researches have created their personal UML profile to be appropriate for equipment level modeling. Some researchers have gone the extra-mile and created a SystemC particular UML profile. Realizing the significance of standardization, THALES and others have submitted, in March 2003, a RFP “Request For concept” to the OMG “Object management group” to standardize a UML particular profile for system modeling. A working group has been shaped and created a methods Modeling Language forum called SysML [15]. The forum has proposed a SysML notation, in response to UML 2.0 edition, to handle the considerations raised within the SE RFP. Like UML, SysML is on its strategy to become an OMG typical principally that loads of UML enhancing dealer equipment have actively participated within the forum and are competing to assist the SysML of their equipment even earlier than it’s absolutely standardized. SysML is designed to be beneficial in specifying requirements, equipment constitution, functional habits, and allocations right through specification and design phases of device engineering. SysML makes use of some UML 2.0 diagrams as is, extends every other UML 2.0 diagrams, and introduces new diagrams to achieve its desires. determine 1 suggests the SysML diagram structure.

determine 1 SysML 1.0 Diagram structure

UML 2.0 diagrams which are reused with out changes: Use Case diagram, Sequence diagram, and State desktop dia­gram. UML 2.0 diagrams that are reused and prolonged: endeavor diagram (extends UML 2.0 pastime diagram), Block Definition dia­gram (extends UML 2.0 type diagram), inner Block diagram (extends UML 2.0 Composite constitution diagram), and Pack­age diagram (extends UML 2.0 kit diagram).

New diagrams which have been brought are: Parametric Constraint diagram, Allocation diagram/Allocation hint potential desk, and Require­ments diagram.

SystemC, as defined through OSCI, is a library of classes and a simulation kernel that prolong typical C++ to permit the modeling of systems by means of featuring hardware constructs in the context of ordinary C++. Being built on commonplace C++ closes the hole between SW and HW designers in addition to providing a stable platform for building of gadget-level equipment. many of the EDA companies are competing to guide SC simulation, synthesis of their design flows. Many semiconductor and programs businesses all started to use SystemC in their design flows. SystemC Language Reference guide (LRM) has been standardized as IEEE 1666 by using the IEEE. SystemC has won the reputation of being advanced at architectural design and architectural verification & HW/SW co-verification as cautioned via Arnout et al. in their SystemC-SystemVerilog evaluation in [1]. This superiority at structure level, besides being C++ based mostly language, suggested SystemC to be the next degree design language to the UML level.determine 2 SystemC Language structure

The different layers of which the SystemC language is composed are shown in figure 2. SystemC offers right here to the clothier:

  • A kernel for event-pushed simulation it is the base infrastructure upon which the movements and tactics can be handled.
  • The ability so as to add any data category the usage of the C++ capacity of inheritance.
  • a collection of primitive channels that may also be used to describe primitive verbal exchange between different modules.
  • a set of very helpful libraries to do verification and function transaction level modeling.
  • a few gadget level design constructing blocks. besides assisting a few predefined hardware information varieties.
  • SystemC design building blocks, as described via its LRM [14] and illustrated in [4], are mainly: modules, ports, interfaces, channels and tactics.

    Modules are the main constructing blocks of the SystemC design. definitely any module is a C++ classification derived from SC_MODULE SystemC type. Any module should still include a collection of ports to talk with different modules, a collection of processes that describe the functionality of each module. inner statistics and channel for keeping the model state and conversation among interior strategies. additionally modules can contain other modules to model the design hierarchy. Interfaces are used to define the set of operations, parameters forms and return values with out specifying how these operations are definitely implemented. These interfaces are used to enable for effortless exploration of different implementations, having the same interface, without having to do many adjustments to the normal fashions.

    The skill for a module to have interaction with different modules via neatly-defined boundaries is constantly said through the inspiration of port. Channels are the implementation of the SystemC interfaces, they outline how the channels behave and how they're implemented. we are able to have a variety of implementations of the of the equal interface, for this reason giving approaches for the designers to discover distinctive communication protocols, having the same interface, with the aid of just altering the interface implementation without affecting the module performance. defined as member capabilities within the modules, procedures are the primary unit of functionality in SystemC. SC_MODULE strategies ought to be registered, by means of SC_METHOD or SC_THREAD name, in the scheduler to be regarded SystemC blocks.

    3. PROPOSED SysML TO SystemC CODE era

    A committed survey has been carried out on each commercial and open supply UML/SysML editing tools to choose the acceptable device for this analysis. ARTiSAN Studio, Rhapsody and Telelogic TAU G2 had been considered to be used in this research. based on the survey outcomes, and for the reason that Rhapsody has been utilized in a few effective equivalent researches [18] and [9], Rhapsody 6.1 device of I-Logix [3] matched our choice standards.

    Many design alternate options have been investigated to be able to put in force the automated SystemC code generation from SysML designs:

    1. traditional UML model method

    This strategy is dependent upon producing XMI mannequin of the Rhapsody design it really is based on UML 1.2 notations. where the UML 2.0 and SysML constructs are represented via stereotypes. The XMI mannequin can then be directly read through one of the template primarily based code generation environments, [2], the place applicable templates should still be utilized to it to generate person personalized SystemC code. The Eclipse fostered mission, OpenArchitectureWare [8], has been recognized as a candidate environment to function the code generation step, but unfortunately it OAW wasn’t able to talk quite simply with Rhapsody 6.1 tool.

    2. Eclipse UML2 model approach

    The Eclipse fostered UML2 undertaking, [17], has created a light-weight finished UML 2.0 facts mannequin it truly is

    anticipated to be adopted because the standard data model between most of the UML provider equipment. OpenArchitectureWare can read and generate Eclipse UML2 information mannequin and generate code out of it by the use of templates as smartly. however alas, Rhapsody 6.1 tool doesn’t generate Eclipse UML2 equivalent models of its designs. So the 2nd approach is to traverse the Rhapsody records model through its API’s and generate the equal Eclipse UML2 information mannequin that may well be then fed to OpenArchitectureWare to apply the templates for code era. This strategy would have doubled the effort towards generating the SystemC code.

    three. Rhapsody API and a vacationer primarily based strategy

    This method depends on accessing Rhapsody 6.1 records mannequin suggestions via its COM API interface. Rhapsody offers numerous ways to access its APIs: through visible basic, VB scripts, VC++, and Java. getting access to the APIs through VC++ has been selected.

    Having accessed Rhapsody SysML design counsel through its API’s, a traveler based mechanism, [2], has been chosen to traverse the SysML design information mannequin, via Rhapsody COM API interface, and generate the applicable SystemC mannequin for each and every element.

    despite the fact the third method is closely dependant on Rhapsody records mannequin and API’s, it has been chosen to conduct this analysis and produce the SystemC fashions. Yet the device has been designed to separate Rhapsody data model traversal from the code generation to enable for instant Eclipse-UML2 information mannequin era in coaching of adopting the 2nd method to be much less stylish on a selected vendor equipment. A prototype has been created to show the visibility of the third approach. The prototype is at the moment capable of generate SystemC code for the constitution SysML requisites, while work is on going to generate the SystemC code for the behavioral SysML necessities. desiring to advantage from the SysML distinct diagrams in visualizing, designing, documenting and validating the equipment mannequin no restrictions were positioned on the styles of the diagrams that should be translated into SystemC. The carried out prototype also creates a makefile in addition to a Microsoft visual Studio 7.1 task for the generated SystemC code to be in a position to bring together and link the generated SystemC code with the SystemC libraries to produce an executable with out the need of the designer manual intervention. In different words the output of the system is a SystemC executable that may also be run to validate the complete equipment, no longer simply a collection of SystemC generated info. The automated era of this makefile and the Microsoft assignment info adopts a template based mostly code era, [2], methodology. Semantically appropriate transformation between SysML design and SystemC generated fashions may be validated by way of trying out the SystemC executable and guaranteeing that it behaves as anticipated for demo SysML code.

    determine 3 SysML/SystemC Translation device

    four. Mapping SysML to SystemC

    A prototype that has been implemented the usage of one in all Rhapsody supplied SysML design examples, the cell HandSet illustration. This SysML illustration has three main blocks: the ConnectionManagementBlock, the MobilityManagementBlock and the DataLinkBlock, apart from two actors the mobile unit, MMI, and the community. figure four shows the high degree structure of the of the cell Handset SysML design with its excessive level blocks and actors. The prototype is capable of generate an executable that models each the constitution and behavioral diagrams of the SysML design. The generated SystemC executable turned into run the sequence of movements method calls have been compared to the expected sequence of activities and techniques calls listed in the provided sequence diagrams to locate them matching. The prototype become run on one other SysML design provided by using Rhapsody, the Radar system design, and produced additionally a successful SystemC specification of the design.

    figure 4 excessive stage architecture of cellular HandSet SysML instance offered with the aid of Rhapsody tool

    The connectivity is carried out in SystemC by way of developing internal SystemC channels like right here code snippet indicates the generated SystemC code the represents this module.

    ConnectionManagementBlock::ConnectionManagementBlock(sc_module_name nm) : sc_module(nm) // Channel/Submodule allocations and connectivity_CallControl = new CallControl("_CallControlInst");_CallControl->setitsConnection(_Connection);_CallControl->setitsCallList(_CallList);_CallControl-> setitsSupplementaryServices(_SupplementaryServices);_CallControl->setitsSMS(_SMS);_CallControl->cc_mm(network);_CallControl->cc_in(call_req);_CallList = new CallList("_CallListInst");_CallList->setitsCallControl(_CallControl);_Connection = new Connection("_ConnectionInst");_Connection->setitsCallControl(_CallControl);_SMS = new SMS("_SMSInst");_SMS->setitsCallControl(_CallControl);_SupplementaryServices = new SupplementaryServices("_SupplementaryServicesInst");_SupplementaryServices-> setitsCallControl(_CallControl);…

    determine 5 Connection administration Block Diagram

    The connectivity of ports is done through SystemC ports via code like:


    whereas each sub-module has setter the way to signify the associations between CallControl module and the relaxation of the modules.

    The dynamic behavior of the SysML can be represented in a lot of diagrams: StateMachine, undertaking, Sequence, and Use Case diagrams as illustrated in figure 6. the following determine represents the state desktop diagram that specifies the dynamic habits of the CallControl SysML block. here code snippet represents the leading formula it truly is generated to model the habits described in the SysML state desktop diagram shown above. The transition and state motion code within the above figure is written within the SysML motion language as detailed by means of Rhapsody. This action language is translated to its equivalent SystemC code. for instance the SysML motion commentary OUT_PORT(cc_mm)->GEN(Disconnect); is translated to cc_mm.write(“Disconnect”); whereas every SystemC module has a dedicated code to intercept the incoming messages like “Disconnect” and fire an interior adventure that SystemC block behavior code will act upon.

    void CallControl::processStatechartOfCallControloutputs() swap(_currentStatechartOfCallControlstate) ConnectionManagement::_eventDisconnect.default_event());spoil;case Idle:// suggests no call in progressif (ConnectionManagement::_eventPlaceCallReq.adventure() == real) _nextStatechartOfCallControlstate.write(energetic);//Actionscc_mm.write("PlaceCallReq");next_trigger(SC_ZERO_TIME);next_trigger();break;// State Idle Actionnext_trigger( ConnectionManagement::_eventPlaceCallReq.default_event());spoil;;

    In modeling the SysML exercise diagram, each undertaking is modeled as a SystemC process while the action language that triggers every undertaking is translated into the relevant SystemC routine that handle technique activation. If the entire habits description of the design is modeled in both the state laptop or the exercise diagrams, the suggestions that live within the sequence diagrams is regarded redundant and signify one other the sequence of movements and operations that the design should go through when a particular event is brought on. This redundant assistance can be used to make certain the typical design is undamaged and goes during the distinct sequence of operations as specified within the set of sequence diagrams. the following determine suggests the sequence of activities and messages which are generated when putting a call is requested.

    The generated SystemC code is with no trouble storing the activities and operations called throughout the SystemC design execution in a correct information constitution. After the execution, the sequence diagrams routine and messages are traversed and in comparison with the sequence of hobbies and operations produced through working the design. If each sequences map to each different, this could mean that SysML/SystemC design is relevant.


    in this analysis, we now have highlighted that using UML notation to model and design a system at a extremely excessive degree has received lots of recognition on the contemporary years. a few UML profiles had been created to support in bridging the hole between the UML notation and device degree design. OMG is fostering SysML as a dedicated system stage UML 2.0 profile. SystemC represents the herbal next stage of gadget abstraction after UML/SysML. SystemC has already become an IEEE general in late 2005. during this analysis, a SysML/SystemC mannequin transformation prototype has been created with very promising outcomes. lots of work has been executed before to utilize UML and SystemC to create system level design ambiance. so far as we understand this analysis is the primary dedicated SysML/SystemC model transformation. A study of the SysML/SystemC mapping and a model transformation prototype has been created with very promising outcomes.


    [1]Guido Arnout and Dennis Brophy, “SystemC and SystemVerilogDesigning SoC together”. Presentation given at the Open SystemC expertise Symposium. San Diego, CA. DAC 2004.

    [2] Krzysztof Czarnecki and Simon Helsen. “Classification of mannequin Transformation tactics”,OOPSLA’03 Workshop on Generative thoughts in the Context of mannequin-pushed architecture.


    [4] Thorsten Grother, supply Martin, Stan Liao, Stuart Swan, “equipment Design with SystemC”. Kluwer tutorial Publishers 2002.

    [5] Martin, furnish, “SystemC and the way forward for Design Languages: opportunities for users and analysis”, complaints of the 16th Symposium on integrated Circuits and methods Design (SBCCI ’03), © IEEE 2003.

    [6] Stephen Mellor, Balcer M., “Executable UML: A basis for mannequin-pushed architecture”, Addison-Wesley, 2003.

    [7] Stephen Mellor, John Wolfe, Campbell McCausland, “Why techniques-on-Chip wants more UML like a gap within the Head”, Design, Automation, and verify convention in Europe, DAC, 2005.


    [9] Ananda Shankar Basu, Marcello Lajolo, Mauro Prevostini. “a strategy for Bridging the gap between UML and Codesign”, UML for SoC Design ebook with the aid of Kluwer/Springer, 2005.

    [10] Riccobene E., Scandurra P., Rosti A. and Bocchio S., “A UML 2.0 Profile for SystemC: towards Highlevel SoC Design”, 5th ACM international convention on Embedded application, 2005.

    [11] Rosenstiel W., Kuhn T., Schweizer T., Winterholer M., Schulz-Key C.. “Object-Oriented Modeling and Synthesis of SystemC necessities”, © IEEE 2004.

    [12] Riccobene E., Scandura P., Rosti A., Bocchio S., “A SoC Design Methodology Involving a UML 2.0 Profile for SystemC”, fifth ACM foreign conference on Embedded software, 2005.

    [13] Michael Butler, Colin Snook “UML-B: Formal modeling and design aided by UML”, ACM Transactions on application Engineering and Methodology, 2006.



    [16] Tan W. H., Thiagarajan P.S., Wong W. F., Zhu Y., Pilakkat S.k., “Synthesizable SystemC Code from UML fashions”, RTSS'04, 2004.

    [17][18] Kathy Dang Nguyen, Zhenxin solar, P.S. Thiagarajan, Weng-Fai Wong, “mannequin-driven SoC Design via Executable UML to SystemC”, RTSS'04, 2004.

    [19] Qiang Zhu, Akio Matsuda, Shinya Kuwamura, Tsuneo Nakata, Minoru Shoji. “An Object-Oriented Design procedure for device-on-Chip the use of UML”. within the 15th Int’l Symp. on equipment Synthesis. Copyright 2002 ACM.

    [20], overseas technology Roadmap for Semiconductors – Design report - 2005

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